David Glasco

David Glasco has been Cadence’s Vice President of the Compute Solutions Group since 2021. In this role, he oversees the design and development of hardware and software for Cadence’s extensive soft IP portfolio which includes the Neo NPU, NeuroWeave AI Compiler, Memory Controllers, Interface Controllers, System IP, NoC, and Chiplet implementation groups.

Before joining Cadence, David held key positions focused on SoC design efforts, including the Tesla FSD SoC, Amazon Kuiper Modem SoC, and Newisys Opteron CC-NUMA SoC. He spent twelve years at NVIDIA, leading various teams responsible for GPU memory system architecture, ISP design, and initiatives within NVIDIA Research. Additionally, he has served on the Technical Advisory Boards of NetSpeed and Terradepth.

David earned his PhD in electrical engineering from Stanford University. He is an accomplished inventor with over 100 patents and numerous publications.